A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18- μħbox m CMOS Technology

—A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme causes the starting phase of gated-oscillators to alternate repeatedly between 0° and 1...

1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuit Using Gated-Oscillators

A burst-mode clock recovery circuit with a novel dual-mode structure is presented. It utilizes two gated-oscillators to align recovered clock edges to data. It can operate in double data-rate mode in which both rising and falling edges of recovered clock are used. To enable this, gated-oscillator reset-phase control scheme is introduced to switch the starting phase of gated-oscillator dynamical...

Burst-Mode Clock Recovery Circuit with a Novel Dual Bit-Rate Structure in 0.n1 8-m CMOS

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gatedII. GATED-OSCILLATOR BASED CLOCK RECOVERY oscillators to align clock with data edges and can operate in GOCRC (Gated-Oscillator based Clock Recovery half-rate clocking mode, doubling data throughput, as well as Circuit) was originally developed for magnetic drum data in full-rate clocking...

A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT

This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and temperature (PVT) variations and to increase the lock range, a frequency locked loop is ...

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling